Analog to digital converter with background calibration techniques
US9912343B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2016 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Dec 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various techniques that can provide a capability to background calibrate ADC linearity error, e.g., due to capacitor mismatch drift and other parameter drift, during normal ADC operation in which analog-to-digital signal conversions are ongoing. A method can include grouping capacitors of an ADC into multiple clusters and calibrating under an arbitrary signal condition. To quickly converge the calibration result, the same arbitrary signal can be converted twice, and the capacitor(s) being calibrated can be modulated after first conversion. The difference between the results of the first and second conversions can contain the error information that can be used for calibration, and the signal component can be removed by this process. These techniques can provide improved linearity at 20-bit level and beyond.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.