Reduction of silicon area for ethernet PFC protocol implementation in queue based network processors
US9912604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2015 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2101/622
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.