Data-plane stateful processing units in packet processing pipelines
US9912610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2015 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Apr 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0864
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.