Delay locked loop
US9917590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2016 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Jun 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.