Multi-level ladder DAC with interconnect between ladder nodes
US9917595B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 5, 2016 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Jul 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/76
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.