Display panel test structure
US9921446B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 3, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136263
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present application discloses a display panel test structure for testing whether signal lines of a display panel are defective, the signal lines at least comprising a plurality of data lines which are divided into N groups, the display panel test structure comprising N first shorting bars arranged in a test area of the display panel, each of which being configured to short-circuit a group of data lines, wherein the display panel test structure further comprises a plurality of first test pads arranged in the test area, each of which connects with one shorting bar corresponding thereto, and each of the first test pads is configured to load a signal to a group of data lines corresponding thereto during a test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.