Low latency interconnect integrated event handling
US9921891B1 · kind B1 · utility
1Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Dec 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/548
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Low Latency Interconnect Integrated Event Handling has been disclosed. In one implementation a hardware based interrupt controller coupled with a hardware based event queue manager, dedicated hardware based queues, and processor instruction extensions allows for off-loading event processing from an operating system thereby dramatically lowering wasted processor cycles while speeding up event processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.