Adaptive diode sizing techniques for reducing memory power leakage
US9922699B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Nov 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for reducing leakage current for a memory array. In various embodiments, techniques are implemented for generating a supply voltage for a memory array which tracks the data retention voltage of the memory array. In one embodiment, multiple diodes are implemented in parallel between a supply voltage and the memory array. The diodes have different sizes and different voltage drops, and the diode which will cause the voltage to drop closest to without going below the data retention voltage is selected for routing the supply voltage to the memory array. Since the data retention voltage for the memory array varies over temperature, the temperature of the system is monitored. Based on changes in the temperature, the system changes which diode is in the circuit path for supplying power to the memory array so as to reduce leakage current for the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.