General four-port on-wafer high frequency de-embedding method
US9922888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | May 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention provides a general four-port on-wafer high frequency de-embedding method. The method comprises: for each on-wafer de-embedding dummy, building a model considering the distributive nature of high frequency characteristics of the on-wafer de-embedding dummy; obtaining the intrinsic Y-parameter admittance matrix of said N on-wafer de-embedding dummies by calculation or simulation by using said models; and solving the equation set which the corresponding measurement and calculation or simulation data of said on-wafer de-embedding dummies satisfy for the elements of the related admittance matrices of the parasitic four-port network to be stripped in de-embedding and model parameters of models on which said calculation or simulation is based.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.