Method and structure for wafer-level packaging
US9922950B2 · kind B2 · utility
3Cited by
10References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2017 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/8181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on the top of the conductive metal pad with the metal core protruding from the surface of the substrate; then, forming an under bump metal layer on the top surface and the side surface of the metal core; and finally, forming a bump structure on the top of the under bump metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.