Semiconductor device including power MOS transistor
US9923091B2 · kind B2 · utility
2Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2017 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
An n-channel power MOS transistor having a gate electrode is formed in an element formation region defined in a semiconductor substrate. A p-type guard ring region is formed in a terminal region. A plurality of p-type column regions are formed from the bottom of the p-type base region to a further deeper position. The column region located in the outermost periphery and the p−-type guard ring region are spaced apart from each other by a distance. A gate electrode lead-out portion electrically coupled to the gate electrode is formed in the p−-type guard ring region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.