Patent · US Active

Fine-grained power gating in FPGA interconnects

US9923555B2 · kind B2 · utility

1Cited by

5References

10Claims

0Family size

Assignee

The Regents of the University of California · US

Inventors

Chengcheng Wang · Beijing, CN
Dejan Markovic · Los Angeles, US

Key dates

Filing date	Mar 14, 2014
Grant date	Mar 20, 2018
Priority date	—
Expiry date	Mar 14, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17772
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.