Self-adaptive analog-to-digital converter
US9923569B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2017 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Sep 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-adaptive SAR ADC techniques that can increase speed and/or decrease its power consumption. In some example approaches, one or more bits from a conversion of a previous sample of an analog input signal can be preloaded onto a DAC circuit of the ADC. If the preloaded bits are determined to be acceptable, bit trials on the current sample can be performed to determine the remaining bits. If not acceptable, the ADC can discard the preloaded bits and perform bit trials on all of the bits. The self-adaptive SAR ADC can include a control loop to adjust, e.g., increase or decrease, the number of bits that are preloaded in a subsequent bit trial using historical data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.