Extent movement speed in multi-tiered systems
US9927991B2 · kind B2 · utility
5Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2016 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Sep 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanism designed to minimize copying of data from one memory tier to another. Data in a first memory location, is addressed based on its logical block address (LBA). When the data is copied into a second cache memory location, the LBA is updated to address the data at the second location. The first memory location is preserved intact. If the data is to be copied back to the first memory location, and the data has not changed since being copied into the second location, the LBA is updated to address the data at the first memory location, and no physical copying of the data from the second location to the first is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.