System and method for an asynchronous processor with token-based very long instruction word architecture
US9928074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2014 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | May 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.