Synchronizing a translation lookaside buffer with page tables
US9928180B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2017 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Feb 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.