Method and system for functional verification and power analysis of clock-gated integrated circuits
US9928323B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2017 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Aug 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for monitoring operation of a design under test (DUT) includes an incoming clock edge input; an outgoing clock edge input; an enable input; a protocol input; an upstream clocking input; and a downstream clocking input. The apparatus also includes a memory in communication with the inputs for storing values from the inputs, and a processor in communication with the memory and the inputs, the processor programmed to determine spurious and missing active clock edges sent from the monitored clock gate. The apparatus also includes a clock categorization output to output the determination of the active clock edges from the monitored clock gate as missing or spurious.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.