Debug architecture
US9928361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2017 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Jun 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.