Device with interconnection structure for forming a conduction path or a conducting plane with high decoupling capacitance
US9929084B2 · kind B2 · utility
1Cited by
2References
14Claims
0Family size
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Key dates
| Filing date | Feb 9, 2017 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Feb 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Electronic device comprising an interconnection structure comprising an alternating stack of arrays of conducting lines and dielectric layers in which:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.