IO power bus mesh structure design
US9929095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2014 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Dec 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS device includes an IO pad ring. The MOS device includes a first IO pad located on a first side of the IO pad ring, and a second IO pad located on a second side of the IO pad ring. The first IO pad includes a metal x layer power interconnect extending in a first direction. The first metal x layer power interconnect is of a metal x layer. The second side is 90° from the first side. The second IO pad includes a second metal x layer power interconnect extending in the first direction. The second metal x layer power interconnect is of the metal x layer. The second IO pad may further include at least one of a metal x+1 layer power interconnect or a metal x−1 layer power interconnect that extends orthogonal to the second metal x layer power interconnect of the second IO pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.