Patent · US Active

Connection propagation for inter-logical block connections in integrated circuits

US9929733B1 · kind B1 · utility

0Cited by

8References

16Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Pratyush Kamal · San Diego, US
Kambiz Samadi · San Diego, US
Jing Xie · Princeton, US
Yang Du · Carlsbad, US

Key dates

Filing date	Feb 21, 2017
Grant date	Mar 27, 2018
Priority date	—
Expiry date	Feb 21, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/975
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.