Semiconductor chip having transistor degradation reversal mechanism
US9933477B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Mar 28, 2014 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Jan 25, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is described that includes monitoring degradation of a semiconductor chip's transistors during normal operation. The method further includes raising an internal voltage of the semiconductor chip in response to the degradation. The method further includes determining that the degradation has reached a threshold. The method further includes triggering application of an elevated temperature to the semiconductor chip so that the degradation is at least partially reversed. The method further includes applying a new lower internal voltage of the semiconductor chip in account of the degradation reversal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.