Integration of V-grooves on silicon-on-insulator (SOI) platform for direct fiber coupling
US9933570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Mar 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B2006/121
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for fabricating a photonic integrated circuit (PIC) comprises providing a wafer comprising an insulator layer positioned between a top semiconductor layer and a base semiconductor layer, patterning the top semiconductor layer to simultaneously define a waveguide and a first etch mask window for forming a fiber-guiding v-groove that substantially aligns to an axis of optical signal propagation of the waveguide, removing a first portion of the top semiconductor layer to form the waveguide according to the patterning, removing a second portion of the top semiconductor layer to form the first etch mask window according to the patterning, and forming the fiber-guiding v-groove according to the first etch mask window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.