Method and apparatus for hybrid chip-level voltage scaling
US9933827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2013 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Mar 11, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various aspects of a power management approach for a system-on-a-chip (SoC) is disclosed herein. In one aspect, the approach includes implementing a power profile for supplying power to a plurality of subsystems on a shared power bus in the SoC. The power profile includes at least one adjustable parameter for controlling the supplied power during an active use state. The approach further includes detecting a power profile change trigger; modifying the power profile based on the power profile change trigger; and adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.