Processors, methods, and systems to implement partial register accesses with masked full register accesses
US9934032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Oct 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.