Display, timing controller and column driver integrated circuit using clock embedded multi-level signaling
US9934715B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Jan 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a timing controller including: a receiving unit configured to receive image data; a buffer memory configured to temporarily store and output the received image data; a timing controller circuit configured to generate a transmission clock signal; and a transmitter configured to receive the transmission clock signal and a transmission data signal, wherein the transmission data signal includes the image data output by the buffer memory, wherein the transmitter is configured to transmit a transmission signal, wherein the transmission clock signal is embedded in the transmission data signal, and wherein the transmission clock signal has a magnitude different from the transmission data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.