Systems and methods for refreshing data in memory circuits
US9934841B1 · kind B1 · utility
3Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Oct 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory refreshing circuit implemented on an integrated circuit comprising a memory circuit that stores original data and an algorithmic data generation circuit that generates write addresses and correct data such that the correct data is stored in the memory circuit at locations that are indicated by the write addresses to correct errors in the original data by overwriting the original data with the correct data during a random access mode of operation of the memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.