Slit stress modulation in semiconductor substrates
US9935000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Feb 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.