Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications
US9935089B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Mar 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/18341
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.