Patent · US Active

Power rail inbound middle of line (MOL) routing

US9935100B2 · kind B2 · utility

2Cited by

9References

15Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Hyeokjin Lim · San Diego, US
Zhengyu Duan · San Diego, US
Qi Ye · San Diego, US
Mickael Malabry · San Diego, US

Key dates

Filing date	Nov 9, 2015
Grant date	Apr 3, 2018
Priority date	—
Expiry date	Nov 9, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/85
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.