Manufacturing methods of thin film transistor having an ohmic contact region and array substrate including the same
US9935177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2015 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Nov 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a thin film transistor and a manufacturing method thereof, an array substrate including the thin film transistor, and a manufacturing method of the array substrate. The thin film transistor comprises an active layer, a gate insulation layer, a gate, an interlayer insulation layer, a source and a drain formed on a base substrate, the interlayer insulation layer and the gate insulation layer are provided therein with through holes corresponding to the source and the drain; the active layer comprises a source ohmic contact region connected with the source, a drain ohmic contact region connected with the drain, a channel region serving as a channel located below the gate, and a lightly doped region between the drain ohmic contact region and the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.