System on chip and correction method of termination impedance element thereof
US9935606B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Dec 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on chip (SoC) and a correction method of termination impedance element thereof are provided. The SoC includes a pad, a first termination impedance element, and a correction circuit. The pad is coupled to an external dynamic random access memory (DRAM) chip, where the DRAM chip includes a corrected termination impedance element. The first termination impedance element is coupled to the pad. The correction circuit is coupled to a control terminal of the first termination impedance element, to control an impedance value of the first termination impedance element. During an initialization period, the correction circuit corrects the impedance value of the first termination impedance element by using the impedance value of the corrected termination impedance element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.