Frequency divider and phase-locked loop including the same
US9935639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2015 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | May 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/54
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider includes a first shifter and a second shifter. The first shifter includes first to M-th clock control components connected together to form a first ring. The control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring. An output of selected clock control components in the first shifter is provided as a carry signal of the first shifter. The second shifter includes first to N-th clock control components connected together to form a second ring. The control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring. An output of selected clock control components in the second shifter is provided as a carry signal of the second shifter. M and N are integers greater than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.