Gain calibration for direct modulation synthesizer using a look-up table searched by a reduced count from an overflow counter
US9935640B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03C3/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to a Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. A calibration unit divides the VCO output and counts pulses. During calibration, the data modulation signal is set to minimum and then maximum values and VCO output pulses counted. A count difference for the data modulation signal at maximum and minimum values is input to a Look-Up Table (LUT) to read out a gain calibration value. During normal operation mode, the gain calibration value from the LUT is applied to a second input of the DAC, which drives the VCO to adjust VCO gain. A switch before the VCO opens the loop for faster open-loop calibration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.