Enabling secured debug of an integrated circuit
US9939074B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2014 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Jan 26, 2035 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB01J2208/00787
- WIPO fieldMechanical elements
- WIPO sectorMechanical engineering
Abstract
Secured debug of an integrated circuit having a test operation mode and a secure mission operation mode. The integrated circuit has a processing unit, a test interface through which the test operation mode is controllable, an on-chip memory which is accessible in the test operation mode and in the secure mission operation mode, and one or more protected resources inaccessible in the test operation mode. The processing unit is configured, in the test operation mode, to receive an authenticated object through the test interface, and store the received authenticated object in the on-chip memory. The processing unit is moreover configured, upon reset into the secure mission operation mode, to execute a boot procedure to determine that the authenticated object is available in the on-chip memory, authenticate the authenticated object, and—upon successful authentication—render the more protected resources accessible to a debug host external to the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.