Counter-based victim selection in a cache memory
US9940246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Oct 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a set-associative cache memory has a plurality of congruence classes each including multiple entries for storing cache lines of data. The cache memory includes a bank of counters, which includes a respective one of a plurality of counters for each cache line stored in the plurality of congruence classes. The cache memory selects victim cache lines for eviction from the cache memory by reference to counter values of counters within the bank of counters. A dynamic distribution of counter values of counters within the bank of counters is determined. In response, an amount counter values of counters within the bank of counters are adjusted on a cache miss is adjusted based on the dynamic distribution of the counter values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.