Streaming interconnect architecture
US9940284B1 · kind B1 · utility
12Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2015 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Jun 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.