Method and apparatus for decimation in frequency FFT butterfly
US9940303B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Mar 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/0003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipelined decimation in frequency FFT butterfly method, and an apparatus to perform this method comprising: a data memory with at least one read port and one write port; an add/subtract unit receiving data from the memory; a multiply/accumulate unit receiving data from the add/subtract unit; a source of coefficients, from logic gates or a coefficient memory, to supply FFT twiddle factors to the multiply/accumulate unit; a shifter receiving data from at least one of the add/subtract unit and the multiply/accumulate unit, the shifter supplying data to the write port of the data memory; wherein the apparatus performs these calculations in four cycles of the add/subtract unit and in four cycles of the multiply/accumulate unit, using complex arithmetic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.