Method for optimizing place-and-routing using a random normalized polish expression
US9940421B1 · kind B1 · utility
2Cited by
5References
29Claims
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Key dates
| Filing date | Oct 10, 2011 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Oct 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/2088
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on a random normalized polish expression, and includes cost considerations based on routing of interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.