Patent · US Active

Firmware security interface for field programmable gate arrays

US9940483B2 · kind B2 · utility

0Cited by

0References

18Claims

0Family size

Assignee

Raytheon Company · US

Inventors

Matthew C. Areno · Round Rock, US
John Hoffman · Fairview, US
William T. Jennings · Plano, US

Key dates

Filing date	Jan 25, 2016
Grant date	Apr 10, 2018
Priority date	—
Expiry date	Jun 12, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F21/74
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

This disclosure provides for implementing a firmware security interface within a field-programmable gate array (FPGA) for communicating between secure and non-secure environments executable within the FPGA. A security monitor is implemented within the programmable logic of the FPGA as a soft core processor and the firmware security interface modifies one or more functions of the security monitor. The modifications to the security monitor include establishing a timer “heartbeat” within the FPGA to ensure that the FPGA invokes a secure environment and raising an alarm should the FPGA fail to invoke such environment.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.