Patent · US Active

Exploiting frame to frame coherency in a sort-middle architecture

US9940686B2 · kind B2 · utility

1Cited by
11References
32Claims
0Family size

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Key dates

Filing dateMay 14, 2014
Grant dateApr 10, 2018
Priority date
Expiry dateAug 1, 2034

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG09G2360/122
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.