Memory cell, memory device, and electronic device having the same
US9940998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2017 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array including a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of complementary bit lines connected to the plurality of memory cells, a plurality of auxiliary bit lines, a plurality of auxiliary complementary bit lines, and a switch circuit. The switch circuit electrically connects the plurality of auxiliary bit lines to the plurality of bit lines during a write operation, electrically connects the plurality of auxiliary complementary bit lines to the plurality of complementary bit lines during the write operation, electrically disconnects the plurality of auxiliary bit lines from the plurality of bit lines during a read operation, and electrically disconnects the plurality of auxiliary complementary bit lines from the plurality of complementary bit lines during the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.