Method for integrated circuit patterning
US9941125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2015 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Feb 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.