Method for exposing polysilicon gates
US9941138B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2014 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Aug 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for exposing polysilicon gate electrodes is disclose. The method comprises planarizing a pre-metal dielectric on a wafer surface; performing a selective etching process to the planarized pre-metal dielectric and a multi-layer dielectric which covers polysilicon gates in the wafer according to pre-set etching parameters to expose the polysilicon gates in the wafer. The selective etching process effectively control the amount of etching, which ensures high surface flatness when exposing the polysilicon gates without affecting the subsequent film deposition process. Therefore, wafer surface defects, gate stack damages, and polysilicon gate deformation caused by the conventional CMP process or the shear stress generated during the CMP process can be avoided, and then product yield can be enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.