PNP-type bipolar transistor manufacturing method
US9941170B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2017 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Mar 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/114
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.