Patent · US Active

Apparatus for design for testability of multiport register arrays

US9941866B2 · kind B2 · utility

0Cited by

5References

27Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Rakesh Vattikonda · San Diego, US
Samrat Sinharoy · San Diego, US
De Lu · Taipei, TW

Key dates

Filing date	Jul 12, 2016
Grant date	Apr 10, 2018
Priority date	—
Expiry date	Dec 22, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318541
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.