Digital-to-analog converter with improved linearity
US9941897B1 · kind B1 · utility
7Cited by
6References
21Claims
0Family size
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Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/42
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.