Scalable interleaved digital-to-time converter circuit for clock generation
US9941898B1 · kind B1 · utility
6Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Dec 27, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Dec 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.