Limit cycle oscillation reduction for digital low dropout regulators
US9946281B1 · kind B1 · utility
4Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | Feb 8, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method achieves minimum limit cycle oscillation (LCO) amplitude of a digital low dropout regulator (D-LDO) by adding auxiliary unit power transistors in parallel with the main PMOS array with selected unit strength and LCO mode. An improved D-LDO with reduced LCO amplitude includes an auxiliary power transistor array in selected strength driven by an output of a comparator in parallel with a main power transistor array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.