Load/store unit for a processor, and applications thereof
US9946547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2006 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Sep 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to the particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.